1. Field of the Invention
Embodiments of the present invention relate to an input buffer of a semiconductor device which detects the voltage level of an input signal during a power-up operation. Priority is claimed of Korean Patent Application No. 2003-84859, filed on Nov. 27, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
2. Description of the Related Art
The power-up sequence of semiconductor devices having dynamic random access memories (DRAMs) includes detecting input signals and driving output pins of the semiconductor devices to a high resistance (Hi-Z) state, before reference voltage signals are applied to the semiconductor devices. The input signals are voltages which control an operational mode of the semiconductor devices in a power-down mode or an active mode, after the semiconductor devices are turned on (powered up). However, in some semiconductor devices, while the reference voltage signals are applied to the semiconductor device after it is powered up, the semiconductor devices may not properly detect the input signals, resulting in erroneous operation of the semiconductor device.
FIG. 1 is circuit diagram illustrating an input buffer of a semiconductor device. The input buffer 100 comprises first and second transistors TR1 and TR2 (forming a current mirror), third and fourth transistors TR3 and TR4 (that receive a reference voltage signal VREF and an input signal CKE), a current source IS (that drives the input buffer 100), and an inverter INV (that outputs an output signal OUTS).
After the semiconductor device is powered up, the input buffer 100 receives the input signal CKE, and should output the output signal OUTS at a low level. Then, in response to the output signal OUTS of the input buffer 100, an output pin (not shown) can be maintained in a high resistance (Hi-Z) state. The voltage level of the input signal CKE is generally lower than the voltage level of the reference voltage signal VREF. Therefore, the input buffer 100 shown in FIG. 1 can output the output signal OUTS at a low level. Then, the output pin (not shown) can be driven to a high resistance (Hi-Z) state. However, before the voltage level of the reference voltage signal VREF reaches a predetermined voltage level after the semiconductor device is powered up, the input buffer 100 may not detect the voltage level of the input signal CKE at a low level.
For example, if the voltage level of the reference voltage signal VREF is 0V right after the semiconductor device is powered up and the voltage level of the input signal CKE is greater than the voltage level of the reference voltage signal VREF, then the input buffer 100 outputs the output signal OUTS at a high level. As a result, the output pin (not shown) may not be able to be driven to a high resistance (Hi-Z) state and the semiconductor device may operate erroneously.